Methods of fabricating conductive traces and resulting structures

ABSTRACT

A method of forming conductive traces comprises forming a seed material over a surface of a substrate, forming a patterned mask material over the seed material to define trenches leaving portions of the seed material within the trenches exposed, and depositing a conductive material over the exposed seed material in the trenches to form conductive traces. At least a portion of the patterned mask material is removed, a barrier formed over side surfaces and upper surfaces of the conductive traces, and exposed portions of the seed material are removed. Conductive traces and structures incorporating conductive traces are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.15/841,660, filed Dec. 14, 2017, pending, the disclosure of which ishereby incorporated herein in its entirety by this reference.

TECHNICAL FIELD

Embodiments disclosed herein relate to methods for fabricatingconductive traces and conductive traces so formed. More specifically,embodiments disclosed herein relate to methods for fabricatingconductive traces for high frequency signal transmission and resultingstructures, including without limitation a redistribution layer (RDL)incorporating such conductive traces and assemblies including such RDLs.

BACKGROUND

The semiconductor industry has, over the years, migrated to the use ofcopper for conductive traces, which metal offers lower electricalresistance, and thus signal impedance, than prior materials such asaluminum or aluminum alloys. This trend has been enhanced by theindustry employing ever-higher frequency signals to accommodate fasterswitching speeds in electrical circuits, in order to maintain powerconsumption at a reasonable level.

One phenomenon associated with the use of copper traces, which isnegligible at lower frequencies but which becomes significant atfrequencies around 1 GHz and above, is the so-called “skin effect”responsive to the surface finish exhibited by the copper trace. Asfrequency increases, the skin effect drives the current into the surfaceof the copper, dramatically increasing power loss and reducing signalspeed with increasing roughness of the surface finish. This is due tothe effective length of the conductor increasing as the current followsalong a rough surface topography of the copper. Thus, at highfrequencies, the effective impedance of the copper increases as afunction of the increased distance the current must traverse over therough copper surface.

Conventional methods of fabricating conductive traces, such as for RDLs,involve depositing a blanket seed layer on a substrate, followed bydepositing and patterning a photoresist, electroplating copper to formtraces in the trenches in the photoresist, and then stripping thephotoresist from the substrate to expose the seed layer, which is thenetched.

The conventional fabrication process is illustrated in FIGS. 1A through1E. In FIG. 1A, a substrate 100 has a seed layer 102 of a metaldeposited, for example, as by physical vapor deposition (i.e.,sputtering), to serve as an adhesion layer and as an electrode forsubsequent electroplating of metal thereon. In FIG. 1B, a layer ofphotoresist 104 is deposited on seed layer 102, after which thephotoresist is patterned, developed and portions of the photoresist 104removed to form trenches 106. In FIG. 1C, copper is electroplated overthe portions of seed layer 102 exposed in the trenches 106 to formconductive traces 108. The photoresist 104 is then removed, exposingconductive traces 108 which exhibit smooth surfaces S from theelectroplating process as shown in FIG. 1D. However, as also shown inFIG. 1D, the portion of seed layer 102 previously covered by patternedphotoresist 104 is now exposed, necessitating removal to avoidelectrical shorting between adjacent conductive traces 108. When seedlayer 102 is removed by wet etching as shown in FIG. 1E, the surfaces ofthe electroplated conductive traces 108 are also etched, resulting inrough surfaces R, increasing conductive trace impedance. As a result,high frequency signal transmission is impaired due to the skin effect,resulting in signal losses and requiring additional power to maintainsignal speed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A through 1E schematically depict a conventional process flow forfabrication of conductive traces on a substrate;

FIGS. 2A through 2G schematically depict a process flow according toembodiments of the disclosure for fabrication of conductive traces on asubstrate;

FIGS. 3A through 3D schematically depict a process flow according toother embodiments of the disclosure for fabrication of conductive traceson a substrate;

FIG. 4A is a schematic top elevation of a conductive trace formedaccording to embodiments of the disclosure;

FIG. 4B is a schematic side elevation of a conductive trace formedaccording to embodiments of the disclosure;

FIG. 4C is a schematic perspective of conductive traces of a level of anRDL formed according to embodiments of the disclosure; and

FIG. 4D is a side schematic partial sectional elevation of an RDLincluding multiple levels of conductive traces formed according toembodiments of the disclosure.

DETAILED DESCRIPTION

Embodiments of the disclosure comprise methods of forming conductivetraces exhibiting smooth surface finishes. Conductive traces so formedsubstantially eliminate the skin effect and exhibit reduced impedancewhen transmitting high frequency signals, enhancing signal transmissionspeed without increasing power requirements.

The following description provides specific details, such as sizes,shapes, material compositions, and orientations in order to provide athorough description of embodiments of the disclosure. However, a personof ordinary skill in the art would understand that the embodiments ofthe disclosure may be practiced without necessarily employing thesespecific details. Embodiments of the disclosure may be practiced inconjunction with conventional fabrication techniques employed in theindustry. In addition, the description provided below does not form acomplete process flow for manufacturing an RDL or other electronicstructure including conductive traces, such a structure includingconductive traces, or assemblies including structures incorporatingconductive traces. Only those process acts and structures necessary tounderstand the embodiments of the disclosure are described in detailbelow. Additional acts to form a complete structure including conductivetraces, or a complete assembly including structures incorporatingconductive traces as described herein may be performed by conventionalfabrication processes.

Drawings presented herein are for illustrative purposes only, and arenot meant to be actual views of any particular material, component,structure, device, or system. Variations from the shapes depicted in thedrawings as a result, for example, of manufacturing techniques and/ortolerances, are to be expected. Thus, embodiments described herein arenot to be construed as being limited to the particular shapes or regionsas illustrated, but include deviations in shapes that result, forexample, from manufacturing. For example, a region illustrated ordescribed as box-shaped may have rough and/or nonlinear features, and aregion illustrated or described as round may include some rough and/orlinear features. Moreover, sharp angles between surfaces that areillustrated may be rounded, and vice versa. Thus, the regionsillustrated in the figures are schematic in nature, and their shapes arenot intended to illustrate the precise shape of a region and do notlimit the scope of the present claims. The drawings are not necessarilyto scale.

As used herein, the terms “comprising,” “including,” “containing,”“characterized by,” and grammatical equivalents thereof are inclusive oropen-ended terms that do not exclude additional, unrecited elements ormethod acts, but also include the more restrictive terms “consisting of”and “consisting essentially of” and grammatical equivalents thereof. Asused herein, the term “may” with respect to a material, structure,feature or method act indicates that such is contemplated for use inimplementation of an embodiment of the disclosure and such term is usedin preference to the more restrictive term “is” so as to avoid anyimplication that other, compatible materials, structures, features andmethods usable in combination therewith should or must be, excluded.

As used herein, the terms “longitudinal,” “vertical,” “lateral,” and“horizontal” are in reference to a major plane of a substrate (e.g.,base material, base structure, base construction, etc.) in or on whichone or more structures and/or features are formed and are notnecessarily defined by earth's gravitational field. A “lateral” or“horizontal” direction is a direction that is substantially parallel tothe major plane of the substrate, while a “longitudinal” or “vertical”direction is a direction that is substantially perpendicular to themajor plane of the substrate. The major plane of the substrate isdefined by a surface of the substrate having a relatively large areacompared to other surfaces of the substrate.

As used herein, spatially relative terms, such as “beneath,” “below,”“lower,” “bottom,” “above,” “over,” “upper,” “top,” “front,” “rear,”“left,” “right,” and the like, may be used for ease of description todescribe one element's or feature's relationship to another element(s)or feature(s) as illustrated in the figures. Unless otherwise specified,the spatially relative terms are intended to encompass differentorientations of the materials in addition to the orientation depicted inthe figures. For example, if materials in the figures are inverted,elements described as “over” or “above” or “on” or “on top of” otherelements or features would then be oriented “below” or “beneath” or“under” or “on bottom of” the other elements or features. Thus, the term“over” can encompass both an orientation of above and below, dependingon the context in which the term is used, which will be evident to oneof ordinary skill in the art. The materials may be otherwise oriented(e.g., rotated 90 degrees, inverted, flipped) and the spatially relativedescriptors used herein interpreted accordingly.

As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise.

As used herein, the terms “configured” and “configuration” refer to asize, shape, material composition, orientation, and arrangement of oneor more of at least one structure and at least one apparatusfacilitating operation of one or more of the structure and the apparatusin a predetermined way.

As used herein, the term “substantially” in reference to a givenparameter, property, or condition means and includes to a degree thatone of ordinary skill in the art would understand that the givenparameter, property, or condition is met with a degree of variance, suchas within acceptable manufacturing tolerances. By way of example,depending on the particular parameter, property, or condition that issubstantially met, the parameter, property, or condition may be at least90.0% met, at least 95.0% met, at least 99.0% met, or even at least99.9% met.

As used herein, the term “about” in reference to a given parameter isinclusive of the stated value and has the meaning dictated by thecontext (e.g., it includes the degree of error associated withmeasurement of the given parameter).

As used herein, the term “smooth” as applied to characterize a surfacefinish of a conductive trace, means and includes a surface finishexhibiting a topography variation, as measured using atomic forcemicroscopy, of no more than about 2 nanometers (nm) RMS. Stated anotherway, a smooth surface will, to the observer, exhibit a mirror finish.

As used herein the term “layer” means and includes a level, film orcoating of material residing on a structure, which level may becontinuous or discontinuous between portions of the material, and whichmay be conformal or non-conformal, unless otherwise indicated.

Referring to FIGS. 2A through 2G, a process flow for forming conductivetraces according to embodiments of the disclosure will be described.

Referring to FIG. 2A, a substrate 200 may comprise a dielectric disposedover existing structures, for example, a semiconductor structure (e.g.,wafer, wafer segment or semiconductor dice), on a semiconductorstructure, on a ceramic, a glass or another carrier substrate. Forexample, in some embodiments, the substrate 200 may comprise an array ofsemiconductor dice (e.g., memory dice) and the traces to be formedthereon will comprise part of an RDL associated with each die. In otherembodiments, the substrate may comprise a sacrificial substrate on whichmultiple RDLs are formed, and subsequently singulated and removed foruse in fabrication of, for example, fan out package (FOP) assemblies.Substrate 200 has a seed material 202, which may be characterized as alayer, of one or more metals deposited thereon, for example, as byphysical vapor deposition, also known as “sputtering.” In oneembodiment, substrate 200 may comprise a glass wafer bearing an organicpolymer formulated for subsequent release of a structure or structuresbearing conductive traces formed thereon by exposure to a laser throughthe glass. Seed material 202 may comprise a single layer of copper, ormay be a bi-layer and comprise a first-deposited layer of, for example,titanium followed by a second layer of copper. The titanium may act toenhance adherence of the to-be-formed conductive traces, as well as abarrier with respect to substrate 200. Seed material 202 may be formed,for example, to a thickness of about 2000 Å.

Referring to FIG. 2B, a layer of mask material, for example a positiveor negative photoresist 204, is deposited on seed material 202, forexample by spin-coating or spray-coating. In one embodiment, a positivephotoresist is employed, as (in comparison to negative photoresists)step coverage is superior, smaller feature size may be achieved and anaqueous developer base may be employed. The photoresist 204 isphotolithographically patterned and developed by conventionaltechniques, and undeveloped portions of the photoresist 204 removed toform trenches 206 exposing portions of seed material 202.

Referring to FIG. 2C, elemental copper is electroplated, the processalso being characterized in the art as electrochemical deposition (ECD)over the portions of the copper of seed material 202 exposed in thetrenches 206 to form conductive traces 208, which may also becharacterized as trace cores, exhibiting smooth side surfaces 210 andupper surfaces 212. By way of example only, conductive traces 208 may beof a height of about 2 μm, and of a width from about 2 μm to about 100μm, widths toward the upper end of the range being more suitable forpower transmission. As formed, the side surfaces 210 and upper surfaces212 exhibit a topography variation of no more than about 2 nanometers(nm) RMS. Characterized another way, the surfaces exhibit a mirrorfinish.

Referring to FIG. 2D, remaining portions of photoresist 204 are dry(i.e., reactive ion) etched to remove a depth of the photoresistmaterial from side surfaces 214 and upper surfaces 216 thereof,incidentally reducing a height of the photoresist 204, but moresignificantly creating gaps 218 between side surfaces 210 of conductivetraces 208 and adjacent side surfaces 214 of photoresist 204. In someembodiments, the width W of gaps 218 may be between about 0.25 μm andabout 2 μm. The gaps 218 must be sufficiently wide, given the aspectratio of the gaps, for the electrodeposition tool employed to ensure theelectrolyte used in the process will reach the bottom of the gaps 218.Stated another way, the etching recesses the photoresist 204 withrespect to the conductive traces 208.

Referring to FIG. 2E, another metal, for example, nickel or gold, isdeposited in gaps 218 and over upper surfaces 212 of conductive traces208 to form etch barrier 220 over side surfaces 210 and upper surfaces212 of conductive traces 208, etch barrier 220 extending downward toseed material 202. Other suitable materials for etch barrier 220include, for example, tantalum, cobalt, indium, TiN, vanadium andcombinations of any of the foregoing. The primary criteria for materialssuitable for barrier 220 is the selectivity of etchants used to removeseed material to those materials over the material of the barrier 220.In addition to protecting conductive traces 208 from etchants, etchbarrier 220 may be used as a base for interconnect metallurgy. Forexample, gold or nickel may serve as a suitable metallurgy forsubsequent formation of an interconnect of compatible metal thereover,or formation of under bump metallization (UBM) for a solder ball.Alternatively, if desirable or required for metallurgical compatibilitywith an interconnect or external connection, upper surfaces 212 ofconductive traces 208 may be selectively masked and another metalelectroplated on barrier 220 at selected locations.

Referring to FIG. 2F, photoresist 204 may be stripped as is conventionalto expose seed material 202 between conductive traces.

Referring to FIG. 2G, seed material 202 is then wet (chemically) etchedbetween conductive traces 208 to electrically isolate conductive traces208 from one another. The etchant employed is selective to the metal ormetals of seed material 202 over the metal of etch barrier 220, whichremains and protects the smooth side surfaces 210 and upper surface 212of conductive traces 208, significantly reducing any adverseconsequences of the above-noted skin effect and preserving signaltransmission speed without the necessity of increasing power. If abi-layer of copper and titanium, or another metal used for adherence toa substrate, is employed, different etchants, each selectiverespectively to copper and titanium (or other metal) over copper areemployed. The underside 222 of traces 208 also presents a smoothsurface, not having been etched. As shown in FIG. 2G, etching of seedmaterial 202 may result in a slight undercut at the bottoms of sidesurfaces 210 below etch barrier 220; however, given the relatively thinseed material 202, the undercut (enlarged for clarity in the drawingfigure) has no significant adverse effect on conductive traces 208 orthe remaining segment of seed material 202 immediately thereunder.

In another embodiment, the process flow is the same as that of thepreceding embodiment in FIGS. 2A through 2C. However, followingformation of conductive traces 208, photoresist 204 is stripped, and asecond photoresist 204′ may be deposited over substrate 200, patternedand developed as shown in FIG. 3A to provide gap 218 of suitable width Wbetween side surfaces 210 of traces 208 and adjacent side surfaces 214′of the portions of photoresist 204′ flanking each trace 208. Photoresist204′ may be the same type (positive or negative) as photoresist 204, andof the same or different composition.

As shown in FIG. 3B, another metal, for example, nickel or gold, isdeposited in gap 218 and over upper surfaces 212 of conductive traces208 to form etch barrier 220 over side surfaces 210 and upper surfaces212 of conductive traces 208, etch barrier 220 extending to downward toseed material 202. Other suitable materials for etch barrier 220include, for example, tantalum, cobalt, indium, TiN, vanadium andcombinations of any of the foregoing. As noted, previously, in additionto protecting conductive traces 208 from etchants, etch barrier 220 maybe used as a base for interconnect or other electrical connectionstructure metallurgy. For example, gold or nickel may serve as asuitable metallurgy for subsequent formation of an interconnect ofcompatible metal thereover, or formation of under bump metallization(UBM) for a solder ball. Alternatively, if desirable or required formetallurgical compatibility with an interconnect or external connection,upper surfaces 212 of conductive traces 208 may be selectively maskedand another metal (e.g., another metal 223) electroplated on barrier 220at selected locations. For brevity and clarity, the another metal (e.g.,another metal 223) is depicted only in FIG. 3B.

As shown in FIG. 3C, photoresist 204′ may be stripped as is conventionalto expose seed material 202 between conductive traces 208.

As shown in FIG. 3D, seed material 202 is then wet etched betweenconductive traces 208 to electrically isolate conductive traces 208 fromone another. The etchant employed is selective to the metal or metals ofseed material 202 over the metal of etch barrier 220, which remains andprotects the smooth side surfaces 210 and upper surface 212 ofconductive traces 208, significantly reducing any adverse consequencesof the above-noted skin effect and preserving signal transmission speedwithout the necessity of increasing power. The underside 222 of traces208 also presents a smooth surface, not having been etched. As shown inFIG. 3D, etching of seed material 202 may result in a slight undercut atthe bottoms of side surfaces 210 below etch barrier 220; however, giventhe relatively thin seed material 202, the undercut (enlarged forclarity in the drawing figure) has no significant adverse effect onconductive traces 208 or the remaining segment of seed material 202immediately thereunder.

FIG. 4A is a schematic top elevation of a portion of a conductive trace208 formed on a substrate 200 according to embodiments of thedisclosure. Etch barrier 220 on side surfaces 210 of conductive trace isdepicted in broken lines, barrier 220 covering upper surface 212 aswell.

FIG. 4B is a schematic side elevation of a portion of a conductive trace208 formed on a substrate 200 according to embodiments of thedisclosure. Barrier 220 on upper surface 212 of conductive trace 208 isdepicted in broken lines, barrier 220 covering side surfaces 210 (oneshown) as well.

FIG. 4C is a schematic perspective of conductive traces 208 of an RDL300, traces 208 being mutually electrically isolated by a dielectricmaterial 302, for example, a polyimide. Barrier 220 covers side surfaces210 and upper surfaces 212 of traces 208.

FIG. 4D is a schematic side elevation of a structure including an RDL300 including multiple levels of conductive traces 208 according toembodiments of the disclosure, each conductive trace having sidesurfaces and upper surfaces covered by a barrier. Traces 208 aremutually electrically isolated by dielectric material 302, varioustraces levels are electrically connected by interconnects 304, otherinterconnects 306 are positioned for connections to semiconductor dice400 on one side of RDL 300, and yet other interconnects comprise UBMs308 having conductive elements in the form of solder bumps 310 disposedthereon for connection of semiconductor dice 400 to higher-levelpackaging 402.

Embodiments of the disclosure include a method of forming conductivetraces, comprising forming a seed material over a surface of asubstrate, forming a patterned mask material over the seed material todefine trenches, leaving portions of the seed material within thetrenches exposed, depositing a conductive material over the exposed seedmaterial in the trenches to form conductive traces, removing at least aportion of the patterned mask material, forming a barrier over sidesurfaces and upper surfaces of the conductive traces, and removingexposed portions of the seed material.

Embodiments of the disclosure also include a method of forming a copperseed material over a surface of a substrate, forming and patterningpositive photoresist material over the copper seed material to definetrenches extending to the copper seed material, electrochemicallydepositing copper over the exposed copper seed material in the trenchesto form conductive traces, etching the patterned positive photoresistmaterial to remove a depth of the photoresist material from at leastside surfaces of the photoresist material adjacent side surfaces of theconductive traces to recess the photoresist material with respect toside surfaces of the conductive traces, electrochemically depositing ametal barrier between the side surfaces of the photoresist material andthe adjacent side surfaces of the conductive traces, and over uppersurfaces of the conductive traces, stripping remaining positivephotoresist material to expose portions of the seed material, andetching the exposed portions of the seed material.

Embodiments of the disclosure further include a structure, comprisingconductive traces mutually electrically isolated by a dielectricmaterial, wherein the conductive traces are configured with arectangular cross-section, comprise a copper core, and side surfaces ofthe copper core and a surface of the copper core extending between theside surfaces are covered with a metal barrier.

While certain illustrative embodiments have been described in connectionwith the figures, those of ordinary skill in the art will recognize andappreciate that embodiments encompassed by the disclosure are notlimited to those embodiments explicitly shown and described herein.Rather, many additions, deletions, and modifications to the embodimentsdescribed herein may be made without departing from the scope ofembodiments encompassed by the disclosure, such as those hereinafterclaimed, including legal equivalents. In addition, features from onedisclosed embodiment may be combined with features of another disclosedembodiment while still being encompassed within the scope of thedisclosure.

What is claimed is:
 1. A method of forming conductive traces, the methodcomprising: forming a seed material extending over a portion of a planarsurface of a substrate; forming a patterned mask material over the seedmaterial to define trenches leaving portions of the seed material withinthe trenches exposed; depositing a conductive material over the exposedseed material in the trenches to form conductive traces; removing atleast a portion of the patterned mask material; forming a barrier overside surfaces and upper surfaces of the conductive traces; after formingthe barrier, removing a remaining portion of the patterned maskmaterial; and removing exposed portions of the seed material.
 2. Themethod of claim 1, wherein: removing at least a portion of the patternedmask material comprises removing a depth of the patterned mask materialat least from side surfaces of the patterned mask material adjacent sidesurfaces of the conductive traces to form gaps between the patternedmask material and the conductive traces; and forming a barrier comprisesforming a barrier in the gaps adjacent the side surfaces and over uppersurfaces of the conductive traces.
 3. The method of claim 1, whereinforming a seed material over a surface of a substrate comprises formingat least a portion of the seed material of copper by physical vapordeposition.
 4. The method of claim 3, wherein depositing a conductivematerial over the exposed seed material in the trenches to formconductive traces comprises electroplating copper in the trenches. 5.The method of claim 4, wherein electroplating copper in the trenchescomprises forming the conductive traces to exhibit a topographyvariation of the side surfaces and the upper surfaces of no more thanabout 2 nanometers (nm) RMS.
 6. The method of claim 5, wherein forming abarrier over side surfaces and upper surfaces of the conductive tracescomprises electroplating nickel, gold, tantalum, cobalt, indium, TiN,vanadium or a combination thereof over the side surfaces and uppersurfaces.
 7. The method of claim 6, further comprising electroplatinganother metal over only a portion of at least one of the upper surfacesof the conductive traces.
 8. The method of claim 3, wherein forming aseed material further comprises forming titanium by physical vapordeposition before forming the at least a portion of the seed material ofcopper thereover.
 9. The method of claim 1, wherein forming andpatterning a mask material over the seed material comprises forming andpatterning a photoresist material.
 10. The method of claim 1, whereinremoving exposed portions of the seed material comprises etching theexposed portions of the seed material with one or more etchantsselective to one or more materials of the seed material over a materialof the barrier.
 11. A method of forming conductive traces, the methodcomprising: forming a seed material extending over a portion of a planarsurface of a substrate; forming a patterned mask material over the seedmaterial to define trenches leaving portions of the seed material withinthe trenches exposed; depositing a conductive material over the exposedseed material in the trenches to form conductive traces; removing all ofthe patterned mask material; forming and patterning another maskmaterial over the seed material to leave gaps between side surfaces ofthe other mask material adjacent side surfaces of the conductive traces;forming a barrier in the gaps adjacent the side surfaces and over uppersurfaces of the conductive traces to completely fill the gaps; and afterforming the barrier, removing the patterned other mask material beforeremoving exposed portions of the seed material.
 12. The method of claim11, wherein the mask material and the other mask material are of thesame composition.
 13. A method of forming conductive traces, the methodcomprising: forming a copper seed material over a surface of asubstrate; forming and patterning positive photoresist material over thecopper seed material to define trenches extending to the copper seedmaterial; electrochemically depositing copper over the exposed copperseed material in the trenches to form conductive traces; etching thepatterned positive photoresist material to remove a depth of thepositive photoresist material from at least side surfaces of thepositive photoresist material adjacent side surfaces of the conductivetraces to recess the positive photoresist material with respect to sidesurfaces of the conductive traces; electrochemically depositing a metalbarrier between the side surfaces of the photoresist material and theadjacent side surfaces of the conductive traces, and over upper surfacesof the conductive traces; stripping remaining positive photoresistmaterial to expose portions of the copper seed material; and etching theexposed portions of the copper seed material.
 14. The method of claim13, wherein electrochemically depositing a metal barrier compriseselectrochemically depositing nickel, gold, tantalum, cobalt, indium,TiN, vanadium or a combination thereof
 15. The method of claim 13,wherein etching the patterned positive photoresist material comprisesreactive ion etching.
 16. The method of claim 13, whereinelectrochemically depositing copper in the trenches comprises formingthe conductive traces to exhibit a topography variation of the sidesurfaces and the upper surfaces of no more than about 2 nanometers (nm)RMS.
 17. A structure, comprising: conductive traces on a seed material;wherein the conductive traces are configured with a rectangularcross-section, comprise a copper core, and side surfaces of the coppercore and a first surface of the copper core extending between the sidesurfaces are covered with a metal barrier, wherein the metal barrierextending along the side surfaces of the copper core stops at a secondsurface of the copper core extending between the side surfaces andopposite the first surface.
 18. The structure of claim 17, wherein themetal barrier comprises nickel, gold, tantalum, cobalt, indium, TiN,vanadium or a combination thereof.
 19. The structure of claim 17,wherein at least some surfaces of the copper core exhibit a topographyvariation of no more than about 2 nanometers (nm) RMS.
 20. The structureof claim 17, wherein the conductive traces and a dielectric materialcomprise a redistribution layer (RDL), and further comprising at leastone semiconductor die electrically connected to at least some of theconductive traces on one side of the RDL.
 21. The structure of claim 20,further comprising conductive elements electrically connected to atleast some of the conductive traces on a side of the RDL opposite the atleast one semiconductor die.
 22. The structure of claim 17, wherein alateral width of the seed material is less than a lateral width of thecopper core.